// Copyright (C) 1953-2021 NUDT
// Verilog module name - cyclestart_control 
// Version: V4.0.20220607
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         global time synchronization 
//         generate report pulse base on global time
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module cyclestart_control 
(
        i_clk           ,
        i_rst_n         ,
        
        i_wr         ,      
        iv_wdata     ,      
        iv_addr      ,    
        i_rd         ,      
              
        o_wr         ,       
        ov_rdata     ,        
        ov_raddr     ,
  
        iv_localclk      ,
        i_syn_ok        ,    
        i_tsn_or_tte    ,  
        
		ov_cycle_length,
        o_cyclestart
);
// clk & rst
input                 i_clk  ;
input                 i_rst_n;

input                 i_wr;
input     [31:0]      iv_wdata;
input     [18:0]      iv_addr;  
input                 i_rd;

output                o_wr; 
output    [31:0]      ov_rdata;  
output    [18:0]      ov_raddr;

input     [79:0]      iv_localclk      ;            // have syned global time 
input                 i_syn_ok        ;
input                 i_tsn_or_tte    ;

output    [31:0]      ov_cycle_length ; 
output                o_cyclestart   ;           // 1024 ms / 1.024ms pluse

wire      [79:0]      wv_oper_base_cpe2pcj ;  
wire                  w_oper_base_en_cpe2pcj ; 
wire      [79:0]      wv_syn_clk ;  
wire                  w_cycle_start_enable;
command_parse_and_encapsulate_cc command_parse_and_encapsulate_cc_inst
(
.i_clk                 (i_clk),
.i_rst_n               (i_rst_n),
                        
.i_wr               (i_wr),
.iv_wdata           (iv_wdata),
.iv_addr            (iv_addr),     
.i_rd               (i_rd),
                        
.o_wr               (o_wr), 
.ov_rdata           (ov_rdata),
.ov_raddr           (ov_raddr),
                       
.ov_cycle_length       (ov_cycle_length),
.o_base_time_wr        (w_oper_base_en_cpe2pcj ), 
.ov_base_time          (wv_oper_base_cpe2pcj   ),
.o_cc_err(),
.o_cc_cfg			   (w_cycle_start_enable   ) 
);
syn_clk_process syn_clk_process_inst(
.i_clk                 (i_clk                  ),
.i_rst_n               (i_rst_n                ),
                                               
.iv_localclk            (iv_localclk             ),
.i_syn_ok              (i_syn_ok               ),
.i_tsn_or_tte          (i_tsn_or_tte           ),
.iv_localclk_cycle      (32'b0       ),
.ov_syn_clk            (wv_syn_clk             )
);

cycle_start_generate cycle_start_generate_inst(
.i_clk                 (i_clk                  ),
.i_rst_n               (i_rst_n                ),
                                               
.iv_localclk            (wv_syn_clk             ),
.i_cycle_start_enable  (w_cycle_start_enable   ),
.i_syn_ok              (i_syn_ok               ),

.iv_cycle_length       (ov_cycle_length),
.iv_base_time          (wv_oper_base_cpe2pcj   ),
.i_base_time_wr        (w_oper_base_en_cpe2pcj ),
.o_cyclestart         (o_cyclestart          )
);

endmodule